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(R)
HA-5101/883
Data Sheet August 17, 2005 FN3931.1
Low Noise, High Performance Operational Amplifier
The HA-5101/883 is a dielectrically isolated operational amplifier featuring low noise and high performance. This amplifier has an excellent noise voltage density of 4.5nV/Hz (max) at 1kHz. The unity gain stable HA-5101/883 yields a 10MHz unity gain bandwidth and a 6V/s slew rate. DC characteristics of the HA-5101/883 assure accurate performance. The 3mV (max) offset voltage is externally adjustable and offset voltage drift is just 3V/C. Low bias currents (200nA max) reduce input current errors and the high open loop voltage gain of 100kV/V, over temperature, increases the loop gain for low distortion amplification. The HA-5101/883 is ideal for audio applications, especially low-level signal amplifiers such as microphone, tape head and preamplifiers. Additionally, it is well suited for low distortion oscillators, low noise function generators and high Q filters.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Noise Voltage @ 1kHz . . . . . . . . . . . 4.5nV/Hz Max * Low Noise Current @ 1kHz . . . . . . . . . . . . . 3pA/Hz Max * Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . 10MHz Min * High Gain (Full Temp) . . . . . . . . . . . . . . . . . .100kV/V Min (Room Temp) . . . . . . . . . . . . . . . . . 1MV/V Typ * Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/s Min * High CMRR/PSRR (Full Temp) . . . . . . . . . . . . . 80dB Min * High Output Drive Capability (Full Temp) . . . . . . . . . 25mA
Applications
* High Quality Audio Preamplifiers * High Q Active Filters * Low Noise Function Generators * Low Distortion Oscillators * Low Noise Comparators
Ordering Information
PART NUMBER HA7-5101/883 5962-89636012A TEMP. RANGE (C) -55 to 125 -55 to 125 PACKAGE 8 Ld CerDIP PKG. DWG. # F8.3A
20 Ld Ceramic LCC J20.A
Pinouts
HA7-5101/883 (CERDIP) TOP VIEW
NC
5962-896360 (CLCC) TOP VIEW
BAL NC NC 20 NC 19 18 NC 17 V+ + 16 NC 15 OUT 14 NC 9 NC 10 V11 NC 12 BAL 13 NC
BAL -IN +IN V-
1 2 3 4
8 7 6 5
NC NC 4 5 6 7 8 V+ OUT BAL
3
2
1
+
-IN NC +IN NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 1994, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HA-5101/883
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . +175C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) Ceramic DIP Package . . . . . . . . . . . . . 120 30 Ceramic LCC Package. . . . . . . . . . . . . 86 26 Package Power Dissipation Limit at +75C for TJ +175C Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.22W Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.35W Package Power Dissipation Derating Factor Above +75C Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . .12.2mW/C Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/C
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55C to +125C Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5V to 15V VINcm 1/2 (V+ - V-) RL 500
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VS= 15V, RS = 100, RL = 500k, VOUT = 0V, Unless Otherwise Specified GROUP A SUBGROUP TEMP (C) 1 2, 3 Input Bias Current +IB VCM = 0V +RS = 100k -RS = 100 VCM = 0V +RS = 100 -RS = 100k VCM = 0V +RS = 100k -RS = 100k V+ = 3V V- = -27V V+ = 27V V- = -3V VOUT = 0V and +10V RL = 2k VOUT = 0V and -10V RL = 2k VCM = +10V V+ =+5V V- = -25V VOUT = -10V VCM = -10V V+ = +25V V- = -5V VOUT = +10V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 4 5, 6 4 5, 6 1 2, 3 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 LIMITS MIN -3 -4 -200 -325 -200 -325 -75 -125 12 12 100 100 100 100 80 80 MAX 3 4 200 325 200 325 75 125 -12 -12 UNITS mV mV nA nA nA nA nA nA V V V V kV/V kV/V kV/V kV/V dB dB
PARAMETER Input Offset Voltage
SYMBOL VIO
TEST CONDITIONS VCM = 0V
-IB
Input Offset Current
IIO
Common Mode Range
+CMR
-CMR
Large Signal Voltage Gain
+AVOL
-AVOL
Common Mode Rejection Ratio
+CMRR
-CMRR
1 2, 3
+25 +125, -55
80 80
-
dB dB
2
FN3931.1 August 17, 2005
HA-5101/883
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VS= 15V, RS = 100, RL = 500k, VOUT = 0V, Unless Otherwise Specified GROUP A SUBGROUP TEMP (C) 1 2, 3 -VOUT1 RL = 2k VS = 18V RL = 600 VS = 18V RL = 600 VOUT = -15V VS = 18V VOUT = +15V VS = 18V VOUT = 0V IOUT = 0mA VOUT = 0V IOUT = 0mA VS = 10V V+ = +10V, V- = -15V V+ = +20V, V- = -15V VS = 10V V+ = +15V, V- = -10V V+ = +15V, V- = -20V Note 4 RL = 2k, CL = 50pF AV = +1V/V 1 2, 3 +VOUT2 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 LIMITS MIN 12 12 15 15 25 25 -6 -6 80 80 80 80 VIO-1 VIO-1 VIO+1 VIO+1 MAX -12 -12 -15 -15 -25 -25 6 6 UNITS V V V V V V V V mA mA mA mA mA mA mA mA dB dB dB dB mV mV mV mV
PARAMETER Output Voltage Swing
SYMBOL +VOUT1
TEST CONDITIONS RL = 2k
-VOUT2
Output Current
+IOUT
-IOUT
Quiescent Power Supply Current
+ICC
-ICC
Power Supply Rejection Ratio
+PSRR
-PSRR
Offset Voltage Adjustment
+VIOAdj
-VIOAdj
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VS= 15V, RS = 50, RL = 2k, CL = 50pF, AVCL = +1V/V, Unless Otherwise Specified GROUP A SUBGROUP TEMP (C) 4 4 4 5, 6 4 5, 6 4 5, 6 -OS VOUT = 0V to -200mV 4 5, 6 +25 +25 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 LIMITS MIN 6 6 MAX 200 400 200 400 35 35 35 35 UNITS V/s V/s ns ns ns ns % % % %
PARAMETER Slew Rate
SYMBOL +SR -SR
TEST CONDITIONS VOUT = -3V to +3V VOUT = +3V to -3V VOUT = 0V to +200mV 10% tR 90% VOUT = 0V to -200mV 10% tF 90% VOUT = 0V to +200mV
Rise and Fall Time
tR
tF
Overshoot
+OS
3
FN3931.1 August 17, 2005
HA-5101/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VS= 15V, RL = 2k, CL = 50pF, AV = +1, Unless Otherwise Specified LIMITS PARAMETER Differential Input Resistance Low Frequency Peak-to-Peak Noise Input Noise Voltage Density Input Noise Current Density Unity Gain Bandwidth Full Power Bandwidth Minimum Closed Loop Stable Gain Output Resistance Quiescent Power Consumption NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2VPEAK). 3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.) 4. Offset adjustment range is [VIO (Measured) 1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. SYMBOL RIN EnP-P En In UGBW FPBW CLSG ROUT PC Open Loop VOUT = 0V, IOUT = 0mA TEST CONDITIONS VCM = 0V 0.1Hz to 10Hz RS = 20, fo = 1000Hz RS = 2M, fo = 1000Hz VO = 100mV VPEAK = 10V NOTES 1 1 1 1 1 1, 2 1 1 1, 3 TEMP (C) +25 +25 +25 +25 +25 +25 -55 to +125 +25 -55 to +125 MIN 250 10 95 +1 MAX 0.2 4.5 3 150 180 UNITS k VP-P nV/Hz pA/Hz MHz kHz V/V mW
TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters Group A Test Requirements Groups C & D Endpoints *PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLES 1 & 2) 1 1*, 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6 1
4
FN3931.1 August 17, 2005
HA-5101/883
tR
tF tR tF
5
FN3931.1 August 17, 2005
HA-5101/883 Burn-in Circuits
CERAMIC MINI-DIP
1 2 3
8
V+
+
7 6 5
C1
C3
D1
V-
4
D2
C2
R1
CERAMIC LCC
NOTES: R1 = 1M, 5%, 1/4W (Min) C1 = C2 = 0.01F/Socket (Min) or 0.1F/Row, (Min) C3 = 0.01F/Socket, 10% D1 = D2 = 1N4002 or Equivalent/Board (V+) - (V-) = 30V
6
FN3931.1 August 17, 2005
HA-5101/883 Schematic
-IN D1 D2 +IN V+
R24 Q24
R25
R23 Q23
R26 Q26 Q47
R60
R28 Q28
Q25 R35 R37 Q37 R36 Q36 R22 Q35 Q21 R20 Q20 Q22 Q19B Q41
QL41 Q45
QL2
R34 Q43
QL1 Q14 Q15
8
Q16
R15 OUTPUT
Q44 Q33
Q46 Q32
Q2A Q2B Q30 Q29 Q38 Q31
Q1B Q1A Q42
Q13
8
R17A Q17
Q19A Q11
Q10 Q27 Q12 R3A Q3
Q5 Q4 Q9 Q34 R4A
3.65K
Q6 Q7
C1
C2 R58 Q8 Q18
3.65K
Q39 R19A R11 R10 R12 R27 R38
830
Q49 Q50 Q48 Q51 R18 V-
R4B
830
R19B
BAL
BAL
7
FN3931.1 August 17, 2005
HA-5101/883 Die Characteristics
DIE DIMENSIONS 70 X 70 X 19 mils 1mil 1790 x 1780 x 483m 25.4m METALLIZATION Type: AI, 1% Cu Thickness: 16kA 2kA GLASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA WORST CASE CURRENT DENSITY: 1.38 x 105A/cm2 SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 54 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5101/883
BAL NC
-IN
V+
+IN
OUT
V-
BAL
8
FN3931.1 August 17, 2005
HA-5101/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
aaa bbb ccc M N
9
FN3931.1 August 17, 2005
HA-5101/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B2 B3 D D1 D2 MIN 0.060 0.050 0.022 0.006 0.342 MAX 0.100 0.088 0.028 0.022 0.358 MILLIMETERS MIN 1.52 1.27 0.56 0.15 8.69 1.83 REF 0.56 9.09 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94
j x 45o
B
E3
E
0.072 REF
0.200 BSC 0.100 BSC 0.342 0.358 0.358 -
5.08 BSC 2.54 BSC 9.09 9.09 5.08 BSC 2.54 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.91 0.08 5 5 20 1.40 1.40 2.41 0.38 9.09 1.27 BSC 8.69
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
D3 E E1 E2 E3 e e1 h j
0.007 M E F S H S B1
0.200 BSC 0.100 BSC 0.015 0.358 0.050 BSC 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015
-E-
L L1 L2 L3 ND NE N
e
L -H-
L3
-FE1 B3
NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.
E2
L2 B2
L1
e1
D1
D2
10
FN3931.1 August 17, 2005
(R)
HA-5101
Data Sheet August 17, 2005 FN3931.1
D E S I GN I N FO R M ATI O N
The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
8
Unless Otherwise Specified: VS = 15V, TA = +25C
1500 INPUT NOISE CURRENT (pA/Hz)
INPUT NOISE VOLTAGE (nV/Hz)
7 6 5 4 3 2 1 0 10 100 1K FREQUENCY (Hz) 10K CURRENT VOLTAGE
OFFSET VOLTAGE (V)
1000
500
100K
0 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
FIGURE 1. NOISE SPECTRUM
FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE
AV = 25,000, VS = 15V (0.09nVP-P RTI) PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz
AV = 25,000, VS = 15V (12.89mVP-P RTO or 0.52VP-P RTI) PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz
11
HA-5101 Typical Performance Curves
20 INPUT OFFSET CURRENT (nA)
Unless Otherwise Specified: VS = 15V, TA = +25C (Continued)
250
BIAS CURRENT (nA)
0
200
150
-20
100
-40
50
-60 -55 -25 0 25 50 75 100 125 TEMPERATURE (C)
0 -55
-25
0
25
50
75
100
125
TEMPERATURE (C)
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
30
5 MAXIMUM
20 SUPPLY CURRENT (mA) OFFSET CHANGE (V) 10 0
4 MINIMUM 3 TYPICAL
2
-10 -20 -30
1
0
50
100
150
200
250
300
350
400
450
500
0
0
2
4
TIME (s)
6 8 10 12 14 SUPPLY VOLTAGE (V)
16
18
20
FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME (NORMALIZED TO ZERO FINAL VALUE) (SIX REPRESENTATIVE UNITS)
FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE
1.1 RISE TIME SLEW RATE (NORMALIZED)
1.1
60 D RISE TIME (NORMALIZED) OUTPUT CURRENT (mA) 50 B 40 30 20 10 0 A B C D 0 C A VIN +15mV -15mV +15mV -15mV 20 40 VOUT 15V 15V 0V 0V 60 80 TIME (s) 100 120 140 160
1.0 SLEW RATE 0.9
1.0
0.9
0.8
0.8
0.7 RL = 2K, CL = 50pF 0.6 -60 -40 -20 0 20 40 60 80 100 120
0.7
0.6
TEMPERATURE (C)
FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE
FIGURE 8. SHORT CIRCUIT CURRENT vs TIME
12
FN3931.1 August 17, 2005
HA-5101 Typical Performance Curves
10M (140) OPEN LOOP VOLTAGE GAIN V/V(dB) VERROR 1M (120)
Unless Otherwise Specified: VS = 15V, TA = +25C (Continued)
1mV
100K (100)
2.65s
10K (80)
5
10
15
18 TIME (1.5s/DIV)
SUPPLY VOLTAGE (V)
FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE
FIGURE 10. SETTLING WAVEFORM
6 CLOSED LOOP VOLTAGE GAIN (dB) 3 0 -3 -6 -9 -12 125C PHASE -55C PHASE 0 -45 -90 -135 AV = 1V/V RL = 2K, CL = 50pF 10K 100K 1M FREQUENCY (Hz) 10M -180 -225 100M 10K 125C GAIN -55C GAIN PHASE SHIFT (DEGREES) 40 30 GAIN (dB) 20 10 0 -10 -20 RL = 2K, CL = 50pF 100K 1M FREQUENCY (Hz) 10M 100M AV = 1 AV = 10 AV = 100
FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND LOW TEMPERATURES
FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY AT DIFFERENT CLOSED LOOP GAINS
13
FN3931.1 August 17, 2005
HA-5101 Typical Performance Curves
140 120 PHASE SHIFT (DEGREES) 100 VOLTAGE GAIN (dB) 80 60 40 20 0 PHASE GAIN 0 45 90 135 180 10 100 1K 10K 100K 1M 10M 100M -120 100 1K 10K FREQUENCY (Hz) 100K 1M REJECTION RATIO (dB) -60
Unless Otherwise Specified: VS = 15V, TA = +25C (Continued)
-40
-PSRR/CMRR
-80 +PSRR -100
FREQUENCY (Hz)
FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCY
FIGURE 14. REJECTION RATIOS vs FREQUENCY
VIN = VOUT = 3V, AV = +1, RL = 2k, CL = 50pF Timescale = 500ns/Div., Scale: Input = 5V/Div, Output = 2V/Div FIGURE 15. SLEW RATE WAVEFORM
Rise Time and Overshoot VIN = VOUT = 0V to +200mV, AV = +1, RL = 2K, CL = 50pF Timescale = 20ns/Div. FIGURE 16. SMALL SIGNAL WAVEFORM
14
FN3931.1 August 17, 2005
HA-5101 Applications Information
Operation At 5V Supply
The HA-5101 performs well at VS = 5V exhibiting typical characteristics as listed below:
ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIAS. . . . . . . . . . . . . . . . . . . . . . . . . . . . AVOL (VO = 3V) . . . . . . . . . . . . . . . . . . VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMRR (VCM = 2.5V) . . . . . . . . . . . . . PSRR (VCC = 0.5V). . . . . . . . . . . . . . . Unity Gain Bandwidth . . . . . . . . . . . . . . Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . 3.7mA 0.5mV 56nA 106kV/V 3.7V 13mA 90dB 90dB 10MHz 7V/s
3 2 4 (NOTE)
Offset Adjustment
The following is the recommended VIO adjust configuration:
+15V 7 + (NOTE) 6 1 RP RP = 100k -15V 5
-
NOTE: Proper decoupling is always recommended, 0.1F high quality capacitor should be at or very near the device's supply pins.
Input Protection
The HA-5101 has built-in back-to-back protection diodes which will limit the differential input voltage to approximately 7V. If the HA-5101 will be used in conditions where that voltage may be exceeded, then current limiting resistors must be used. No more than 25mA should be allowed to flow in the HA-5101's input.
Comparator Circuit
V+ RLIM 2 7
VIN
RLIM 3 + 4 V-
6
Output Saturation
When an op amp is overdriven, output devices can saturate and sometimes take a long time to recover. Saturation can be avoided (sometimes) by using circuits such as:
V+ R1 R2 +
Choose RLIM Such That:
( V IN MAX - 7V ) ---------------------------------------------- 2R LIM 25mA
R3 IN VSOURCE R4 V-
If saturation cannot be avoided the HA-5101 recovers from a 25% overdrive in about 6.5s (see photo).
OUT
Top: Input Bottom: Output, 5V/Div., 2s/Div. Output is overdriven negative and recovers in 6s.
15
FN3931.1 August 17, 2005
HA-5101
TABLE 1. TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized At: VS = 15V, RL = 2k, CL = 50pF, AVCL = +1V/V, Unless Otherwise Specified PARAMETER Offset Voltage Offset Voltage Average Drift Offset Current Average Drift Input Bias Current Input Offset Current Differential Input Resistance Input Noise Voltage Density VCM = 0V Versus Temperature Versus Temperature VCM = 0V VCM = 0V VCM = 0V fo = 10Hz fo = 100Hz fo = 1kHz Input Noise Current Density fo = 10Hz fo = 100Hz fo = 1kHz Large Signal Voltage Gain VOUT = 10V TEST CONDITIONS TEMP (C) +25 -55 to +125 -55 to +125 +25 +25 +25 +25 +25 +25 +25 +25 +25 -55 +25 +125 Slew Rate Full Power Bandwidth Rise and Fall Times Overshoot Settling Time VOUT = 3V VPEAK = 10V, (Note 2) VOUT = 200mV VOUT = 200mV To 0.1% for 10V Step To 0.01% for 10V Step Output Short Circuit Current Output Resistance Supply Current Minimum Supply Voltage t < 10s, VOUT = 15V Open Loop No Load Functional Operation Only, Other Parameters Will Vary -55 to +125 -55 to +125 -55 to +125 -55 to +125 +25 +25 +25 +25 +25 +25 TYP 0.8 3 100 65 35 500 5.4 3.4 3.2 6 1.5 0.52 400K 1M 1M 10 159 50 20 4.5 6 35 110 4.3 4 DESIGN LIMITS Table 1 7 250 Table 1 Table 1 Table 3 9 5.5 Table 3 20 5 Table 3 Table 1 Table 1 Table 1 5.4 85 Table 2 35 6 10 50 Table 3 Table 1 5 UNITS mV V/C pA/C nA nA k nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz V/V V/V V/V V/s kHz ns % s s mA mA V
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FN3931.1 August 17, 2005

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